Electronic data systems are frequently interconnected using network communication systems. Networks and channels are two approaches that have been developed for computer network architectures. Traditional networks (e.g., LANs and WANs) offer flexibility and relatively large distance capabilities. Channels, such as the Enterprise System Connection (ESCON) and the Small Computer System Interface (SCSI), have been developed for high performance and reliability. Channels typically use dedicated short-distance connections between computers or between computers and peripherals.
Features of both channels and networks have been incorporated into a network standard known as xe2x80x9cFibre Channel,xe2x80x9d which is defined by American National Standards Institute (ANSI) specifications, such as X3.230 (1994). Fibre Channel systems attempt to combine the speed and reliability of channels with the flexibility and connectivity of networks.
Data in a Fibre Channel network is transported in packets, which may be two kilobytes or smaller. These packets,of data are referred to as xe2x80x9cframes.xe2x80x9d xe2x80x9cSequencesxe2x80x9d include one or more frames. Frames in a sequence must be assembled at the receiving device in a predetermined order before the sequence can be considered complete.
A processor in the receiving device may validate each received frame. Validation may include checking the frames for errors and determining whether the frames are being received in the correct sequence. The processor may not be able to perform this validation as quickly as the frames are received, e.g., at xe2x80x9cwire speed.xe2x80x9d Validation may require a significant amount of post processing and consume processor resources.
A device in a Fibre Channel network may include a frame receive queue coupled to a node port. The frame receive queue may receive frames from the node port and extract the Start-of-Frame(SOF) and End-of-Frame (EOF) delimiters for the frame and the header and first eight words in the payload (PLW 0-7). The frame receive queue may alternate the storing of this information between two memory banks. Frame validation circuitry may use the information in the memory banks to perform consistency checks on received frames and produce a result for each frame.
Each received frame may be associated with a buffer number, which may serve as a partial address for the frame. An address generator may use the buffer number to generate an address for a random access memory (RAM) in which the SOF, EOF, header, and PLW 0-7 for the frame are stored. The address generator may also use the buffer number to generate an address for a local memory in which the payload for the frame is stored.
The frame receive queue may generate an entry including the SOF, EOF, buffer number, and validation results for the frame. The entry may be stored in a completion RAM in the frame receive queue.